Work 
D-Map Cache
Designed and developed a simple Direct Mapped CPU cache for the CFU Proving Ground RISC-V implementation.
RISC-VVerilogFPGAArchitecture
What's the point of adding such a simple cache?
The cache provides a simplified model of a cached memory hierarchy, allowing experiments with temporal and spatial locality and the performance impact of cache-aware versus cache-unaware memory-access patterns.
Helpful Links
Draw Diagram of Current SoC setup!!
Address Slicing (Maybe Replace With Hand Drawing)
Tag Index
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Explain FSM!!
| Original | Mine |
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